Santa Clara, California--(Newsfile Corp. - August 2, 2022) - Avery Design Systems today announced that its fully-tested Verification IP (VIP) for 800Gbps Ethernet can now be used to perform virtual network co-simulation for the full layer Ethernet 2-7 network stack. The combination of the VIP and a virtual co-simulation/co-emulation system enables the running of full hardware/software system verification on pre-silicon SoC RTL and software integrations. System designers can now perform system-level validation of an SoC design's Ethernet and TCP/IP network interfaces using real network traffic workloads of communication, datacenter, and storage network protocols running on either host OS or virtual machine (guest OS) platforms.
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Key Takeaways:
- Avery Design System's Ethernet VIP can now perform virtual network co-simulation for the full layer Ethernet 2-7 network stack.
- Avery Design Systems announces CXL3.0 VIP
- Solid state storage controller startup, TenaFe, leverages Avery VIP for time to market and verification advantages
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Avery Design Systems Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential back tracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information is available at www.avery-design.com.
Contacts:
Christopher Browy
(978) 851-3627
cbrowy@avery-design.com
Mike Sottak
(650)248-9597
mike@wiredislandpr.com
Source: Avery Design Systems
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